Moore’s Law Has Left the Building — and Added Another Floor.

For the better part of a decade, we have been hearing that Moore’s Law is dead—or at least wheezing badly enough that someone should call hospice. The basic problem is easy to understand. For roughly half a century, the semiconductor industry kept making computers better by shrinking transistors and squeezing more of them onto the same piece of silicon. Eventually, however, you begin running out of “smaller.” Atoms, it turns out, are not terribly cooperative when engineers ask them to move over a little.

But IMEC, the Belgian research institution that works years ahead of commercial production with the world’s leading chipmakers, has published a roadmap extending semiconductor scaling well into the 2040s. IMEC is not literally the boss of Intel, Taiwan Semiconductor Manufacturing Company or Samsung, but it is one of the places where the industry works out which technologies may actually be manufacturable ten or fifteen years from now. Its roadmap suggests Moore’s Law may not be dying at all. It may simply be changing direction.

Almost every meaningful leap in modern technology has depended on getting more computing power from less space and less electricity. Faster phones, cheaper computers, cloud computing, self-driving vehicles and, of course, artificial intelligence all trace back to the same underlying engine: more transistors, arranged more efficiently. We spend plenty of time talking about the applications sitting on top of the technology stack. Meanwhile, the semiconductor industry is still busy rebuilding the basement.

The first major change is expected around 2033 with a device called a complementary field-effect transistor, mercifully shortened to CFET. Today’s logic chips use two complementary types of transistors, called nMOS and pMOS, generally positioned beside one another. A CFET turns that arrangement on its side and stacks one above the other.

Instead of continuing to fight for every last fraction of horizontal space, chipmakers begin using the third dimension. IMEC expects CFETs to enter its roadmap at the A7 generation, with the architecture eliminating much of the spacing that currently separates the two transistor types. In plain English, roughly the same footprint can hold considerably more logic.

The idea is not entirely new. The first serious demonstrations began in the 1980s and continued into the early 1990s. Fujitsu researchers demonstrated vertically layered CMOS devices using laser recrystallization in 1983. Mitsubishi Electric researchers were describing the basic technologies required for three-dimensional integrated circuits by 1986. Matsushita, now Panasonic, later worked on four-layer 3D integrated circuits for parallel image processing. Siemens and Fraunhofer also pursued a vertical inter-chip project from 1993 through 1996.

Then there was Dense-Pac Microsystems, a small-cap darling for a while during the 1990s. The company manufactured proprietary three-dimensional, high-density memory products and promoted chip stacking as the future. The future, unfortunately, did not arrive on Dense-Pac’s schedule. The technology never became the mass-market breakthrough investors envisioned, and the company eventually changed direction. These efforts were not CFETs in the modern sense, but they were early attempts to escape the flatland of conventional chip design.

So why didn’t we all have vertically stacked supercomputers in our pockets by 1997? Because demonstrating something in a laboratory and producing billions of reliable transistors at an acceptable cost are two very different exercises. Stacking active devices creates problems involving heat, alignment, electrical connections, manufacturing temperatures and production yield. If one layer is defective, the entire structure may become expensive scrap.

Those earlier experiments proved the concept could work. They did not yet provide the tools, materials, lithography or process control necessary to turn it into a mass-market manufacturing platform.

That is what is different today. The industry already uses forms of vertical integration in memory, advanced packaging and chiplets. Gate-all-around transistors are moving into production, backside power delivery is being developed, and increasingly sophisticated lithography can create structures that would have looked absurdly ambitious thirty years ago. CFET is less a sudden science-fiction leap than the next floor being added to a building the industry has been quietly reinforcing for years.

In practical terms, that could mean more capable chips without physically larger devices or dramatically larger batteries. More artificial intelligence processing could happen locally on a phone, automobile or robot instead of requiring every calculation to make a round trip to a data center. Computers could perform more work per watt, which matters not only for battery life but also for the enormous power requirements now associated with AI infrastructure. The limiting resource in computing is increasingly not raw intelligence but electricity.

Then comes the even more exotic part. Around 2041, IMEC’s roadmap contemplates replacing the silicon conduction channels inside advanced transistors with two-dimensional semiconductor materials. These materials, including compounds such as molybdenum disulfide and tungsten disulfide, can form crystalline layers roughly 0.7 nanometers thick—essentially an atomic sheet.  Silicon loses performance when its channel becomes too thin. Certain 2D materials may remain electrically useful at dimensions where silicon begins behaving badly, allowing engineers to maintain tighter control over the flow of current while reducing leakage and power consumption.

There are still enormous obstacles. Producing uniform atomic layers across 300-millimeter wafers, attaching reliable electrical contacts, integrating insulating materials and achieving both n-type and p-type performance are not solved problems. A roadmap is not a promise, and 2041 is a long way from a commercial purchase order.

Still, semiconductor progress has never occurred because the problems were easy. It has occurred because the economic rewards for solving them are almost incalculable.

Perhaps Moore’s Law is not dead. Perhaps we have simply reached the point where shrinking in two dimensions is no longer enough. The next era of computing will be built by stacking transistors, redesigning chips as three-dimensional systems and eventually replacing some of the silicon itself with materials only an atom or two thick.

Moore’s Law is not shrinking anymore. It is stacking.

As always, if you would like to talk about how this may affect your portfolio, or how we are thinking about AI, infrastructure, software, and the companies powering this next wave, please give us a call. Your capital, our expertise, a bespoke creation.